/*
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 * Gary Jennejohn <gj@denx.de>
 * David Mueller <d.mueller@elsoft.ch>
 *
 * Configuation settings for the SAMSUNG SMDK2410 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/

/*by hugerat ,phase 1---------------------------------------------*/
#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */
#define CONFIG_OK2440 1 /* on a SAMSUNG rat2440 Board */
#define CONFIG_OK2440_LED 1 /* Use the LED on Board */
//#define	CONFIG_S3C2410		1	/* in a SAMSUNG S3C2410 SoC     */
//#define CONFIG_SMDK2410		1	/* on a SAMSUNG SMDK2410 Board  */
/*----------------------------------------------------------------*/
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ	12000000/* the 2410 or 2440 has 12MHz input clock */


#define USE_920T_MMU		1
#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */

/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

/*
 * Hardware drivers
 */

/*by hugerat ,phase 2-------------*/
//#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
//#define CS8900_BASE		0x19000300
//#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */


#define CONFIG_DRIVER_DM9000		1
#define CONFIG_DM9000_USE_16BIT 	1
#define CONFIG_DM9000_BASE			0x20000300
#define DM9000_IO					0x20000300  
#define DM9000_DATA					0x20000304
/*---------------------------------*/

/*
 * select serial console configuration
 */
#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SMDK2410 */

/************************************************************
 * RTC
 ************************************************************/
#define	CONFIG_RTC_S3C24X0	1

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE		115200


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF

/*by hugerat,phase 2---------*/
#define CONFIG_CMD_PING
/*---------------------------*/
/*by hugerat,phase5--------*/
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_TAG
/*向linux内核传递函数所需的宏*/
/*----------------------------*/
/*by hugerat,phase 3---------*/
//nand Flash param

#define CONFIG_CMD_NAND

#define CONFIG_CMDLINE_EDITING

#ifdef CONFIG_CMDLINE_EDITING
#undef CONFIG_AUTO_COMPLETE
#else
#define CONFIG_AUTO_COMPLETE
#endif

//#define CONFIG_NAND_LEGACY 
//不使用LEGACY,以使用自带的nand flash驱动
/*
 * NAND flash settings
 */
#if defined(CONFIG_CMD_NAND)
#define CFG_NAND_BASE 0x4E000000 
/* NandFlash控制器在SFR区起始寄存器地址 */
#define CFG_MAX_NAND_DEVICE 	1	
/* Max number of NAND devices		*/

#define CONFIG_MTD_NAND_VERIFY_WRITE 1 //使能flash写校验


/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
#endif	/* CONFIG_CMD_NAND */

/*---------------------------*/

#define CONFIG_BOOTDELAY	2
#define CONFIG_BOOTARGS	"noinitrd root=/dev/nfs nfsroot=192.168.1.10:/opt/root_nfs ip=192.168.1.70:192.168.1.10:192.168.1.10:255.255.255.0:mini.arm9.net:eth0:off init=linuxrc console=ttySAC0"
#define CONFIG_ETHADDR	08:00:3e:26:0a:5b  /*by hugerat,phase 2,原句是被注释掉的。*/
#define CONFIG_NETMASK          255.255.255.0
#define CONFIG_IPADDR		192.168.1.70 /*by hugerat,phase 2,改变默认的IP地址*/
#define CONFIG_SERVERIP		192.168.1.80 /*by hugerat ,phase 2,改变原服务器IP地址*/
/*#define CONFIG_BOOTFILE	"elinos-lart" */
#define CONFIG_BOOTCOMMAND	"tftp 0x31000000 uImage;bootm 0x31000000" 

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP				/* undef to save memory		*/
#define	CFG_PROMPT		"mini2440 # "	/* Monitor Command Prompt	*/
#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/

#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */

#define	CFG_LOAD_ADDR		0x31000000	/* default load address	bootm use it*/

/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
/* it to wrap 100 times (total 1562500) to get 1 sec. */
#define	CFG_HZ			1562500

/* valid baudrates */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */

#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */

#define CFG_FLASH_BASE		PHYS_FLASH_1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
/*by hugerat,phase 1------------*/
//#define CONFIG_AMD_LV400	1	/* uncomment this if you have a LV400 flash */
//#if 0
//#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
//#endif
#define CFG_NO_FLASH		1

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */

/*by hugerat,phase 3------------*/
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_OFFSET 0x30000
//#define CFG_ENV_OFFSET 0X30000

//#define	CONFIG_ENV_IS_IN_FLASH	1
/*------------------------------*/
#define CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */

/*by hugerat ,phase 1-----------------------------------------*/
# if defined(CONFIG_OK2440_LED) 
/* GPIO */
#define GPIO_CTL_BASE 0x56000000
#define oGPIO_f 0x50
#define oGPIO_CON 0x0 /* R/W, Configures the pins of the port */
#define oGPIO_DAT 0x4 /* R/W, Data register for port */
#define oGPIO_UP 0x8 /* R/W, Pull-up disable register */


#endif
/*------------------------------------------------------------*/
/*by hugerat,phase 4------------------*/
#define STACK_BASE 0x33f00000
#define STACK_SIZE 0x8000

/* NAND Flash Controller */
#define NAND_CTL_BASE 0x4E000000
#define bINT_CTL(Nb) __REG(INT_CTL_BASE + (Nb))
/* Offset */
#define oNFCONF 0x00

# if defined(CONFIG_S3C2440)
#define CONFIG_S3C2440_NAND_BOOT 1
/* Offset */
#define oNFCONT 0x04
#define oNFCMD 0x08
#define oNFADDR 0x0c
#define oNFDATA 0x10
#define oNFSTAT 0x20
#define oNFECC 0x2c
#define rNFCONF (*(volatile unsigned int *)0x4e000000)
#define rNFCONT (*(volatile unsigned int *)0x4e000004)
#define rNFCMD (*(volatile unsigned char *)0x4e000008)
#define rNFADDR (*(volatile unsigned char *)0x4e00000c)
#define rNFDATA (*(volatile unsigned char *)0x4e000010)
#define rNFSTAT (*(volatile unsigned int *)0x4e000020)
#define rNFECC (*(volatile unsigned int *)0x4e00002c)

#endif

# if defined(CONFIG_S3C2410)
#define CONFIG_S3C2410_NAND_BOOT 1
/* Offset */
#define oNFCONF 0x00
#define oNFCMD 0x04
#define oNFADDR 0x08
#define oNFDATA 0x0c
#define oNFSTAT 0x10
#define oNFECC 0x14
#define rNFCONF (*(volatile unsigned int *)0x4e000000)
#define rNFCMD (*(volatile unsigned char *)0x4e000004)
#define rNFADDR (*(volatile unsigned char *)0x4e000008)
#define rNFDATA (*(volatile unsigned char *)0x4e00000c)
#define rNFSTAT (*(volatile unsigned int *)0x4e000010)
#define rNFECC (*(volatile unsigned int *)0x4e000014)
#define rNFECC0 (*(volatile unsigned char *)0x4e000014)
#define rNFECC1 (*(volatile unsigned char *)0x4e000015)
#define rNFECC2 (*(volatile unsigned char *)0x4e000016)
#endif
/*----------------------------------------------------*/

#endif	/* __CONFIG_H */
